5. Conclusion 4. Experimental Results

the numbers of nodes of the original and optimized circuits after being cleaned up by SIS command " sweep " and then decomposed into AND/OR gates. (2) # FFs (orig. / opt.): the numbers of flip-flops in the original and optimized circuits. For instance, s13207 has 490 flip-flops, but only 453 left in the optimized circuit. (3) # equiv. internal pairs (comb / seq): the number of internal signal pairs that are identified as combinationally equivalent and sequentially equivalent in our program respectively. Identifying these pairs play an important role in reducing the run-time complexity. (4) # equivalent FF-pairs (comb. / seq.): the numbers of equivalent flip-flop pairs that are verified as combinationally equivalent and sequentially equivalent respectively. Among the (490 / 453) flip-flops of original and optimized s13207, 419 pairs are identified as equivalent using our program, where 379 pairs are combination-ally equivalent and 40 pairs are sequentially equivalent. (5) # equivalent PO-pairs (comb. / seq.): the numbers of combinationally and sequentially equivalent primary output pairs. The verification time on a Sun-sparc5 with 128-Mbyte memory in seconds is given in the last column. Table 2 shows the results of using our program to verify the circuits after sequential redundancy removal. Among the total 23 circuits, thirteen (including s1423, s5378 and s9234) are sequentially equivalent instead of combina-tionally equivalent to their original version. It is worth mentioning that, to our knowledge, no pure FSM-traversal technique has successfully verified the ISCAS89 benchmark circuits larger than s1423. Existing state-traversal-based verification approaches for equivalence checking are subject to combinatorial explosion, and thus, only applicable to small to medium-sized circuits. In an attempt to handle larger circuits, we propose a hybrid method that combines the advantages of local BDD-based and ATPG-based approaches. To speed up the verification process, we devise a robust engine to explore the sequential similarity between circuits under verification based on the idea of partial justification. Because of using local BDD's, our approach is less sensitive to the degree of Circuit # nodes original / optimized # FFs orig. / opt. # internal eq. pairs (comb / seq.) # equivalent FF-pairs (comb. / seq.) # equivalent PO-pairs (comb. / seq.) * Redundancy removed circuits that are sequentially equivalent, but not combinationally equivalent, to their original version. structural similarity as compared to the pure ATPG-based approaches. We presented the experimental results of verifying large ISCAS89 benchmark circuits that have been fully optimized …